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ver1.0 1 LD1071 16 channel output led driver with 14 bit pwm controller LD1071 16 channel output led dr iver with 14 bit pwm controller ver. 1.0 / mar. 2009 this document is a general product descriptio n and is subject to change without notice. ldt inc. does not assume any responsibility for use of circuits described. LD1071 16 channel output led driver with 14 bit pwm controller
ver1.0 2 LD1071 16 channel output led driver with 14 bit pwm controller LD1071 revision history 2009.03.12 -first version 1.0 transfer date contents version
ver1.0 3 LD1071 16 channel output led driver with 14 bit pwm controller the LD1071 is specifically designed for led and le d display applications using pwm(pulse width modulation) control with 14 bit color depth. the LD1071 provides a consta nt output current for driving the leds against for the variation of led forward voltage( vf ). the constant output current can be preset through an external resistor. more over, the preset output current with external resistor can be programmed up to 256 levels for led global brightness adjustment. the LD1071 consists of 16 bit shift registers, latches, and-gates, constant current driver and 14 bit pwm controller. features ? output current : set-up at 5ma to 45ma with an external resistor ( when vdd=3.3v, iout : 5ma ~ 30ma ) ? include error detection circuit ? 16 constant current output channels ? 14 bit gray scale pwm control ? 8 bit programmable output current control ? constant current accuracy - pin to pin deviation : < ? 3% (max) - chip to chip deviation : < ? 6% ( max) ? 3.3v / 5v cmos compatible input ? package : LD1071-sp (sop-24), LD1071-ss (ssop-24) ? maximum clock input frequency : 25mhz ? maximum pwmck input frequency : 25mhz description pin description pin no. pin name description 1 gnd ground signal 2 din serial input data 3 clock shift input clock for serial input data din( rising edge clocking) 4 strobe data strobe signal. this pin is a pull-down type. 24 vdd power supply signal (3.3v/5v) 21 pwmck pwm gray scale clock signal. this pin is a pull-up type. 22 dout serial data output 23 rext connect the resistor between this pin and gnd to set up the constant output current for all the outn. 5~12 13~20 outn constant current outputs, n = 0 ~ 15 pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 gnd din clock strobe out0 out1 out2 out3 out4 out5 out6 out7 vdd rext dout pwmck out15 out14 out13 out12 out11 out10 out9 out8
ver1.0 4 LD1071 16 channel output led driver with 14 bit pwm controller block diagram iref dac out0 out1 out15 * * * rext pwmck strobe din clock dout LD1071 14 bit counter 16 bit shifter register 16 bit display data register 16 bit display data register 16 bit display data register 16 bit display data register 16 bit configuration register comparator comparator comparator comparator 16 bit error status * out14 strobe control 16 16 16 16 16 16 16
ver1.0 5 LD1071 16 channel output led driver with 14 bit pwm controller absolute maximum ratings (ta = 25 o c) parameter symbol rating unit supply voltage output voltage output current input voltage gnd terminal current clock frequency power dissipation operating temperature storage temperature v dd v out i out v in i gnd f ck p d t opr t stg 0~7.0 -0.5~13.5 450 -0.4~v dd +0.4 960 25 1.67 -40~85 -55~150 v v ma v ma mhz w o c o c pwmck frequency f pwmck 25 mhz sop 1.48 ssop thermal resistance ( on pcb, ta = 25 ? ) r th(j-a) 75 ? /w sop 85 ssop electrical characteristics
ver1.0 6 LD1071 16 channel output led driver with 14 bit pwm controller dc characteristics symbol unit input voltage v ih v max. v dd typ. - min. 0.8v dd recommended operatin g conditions ?h? level v il 0.2v dd - gnd ?l? level output voltage v ol v 0.2v dd - - dout v oh - - 0.8v dd supply voltage v dd v 5.5 5 4.5 led driver output voltage v out v 13.5 high level output current i oh ma -1 low level output current i ol ma 1 led driver output current i out ma 20 operating free-air temperature range o c 85 -40 clock frequency f ck mhz 25 pwmck frequency f pwmck mhz 25 setup time t setup ns 15 ac characteristics symbol unit max. typ. min. pulse width t wh0 / t wl0 ns 20 clock t wh1 ns 40 pwmck t wh2 ns 40 strobe hold time t hold ns 15 f pwmck mhz 20 @5v @3.3v
ver1.0 7 LD1071 16 channel output led driver with 14 bit pwm controller electrical characteristics (vdd = 5v, ta = 25 o c) 7.0 4.5 - rext=500 ? , outn=off ref=ffh, pwm=gray0 ioff2 ma 0.8 0.4 - rext=open, outn=off ref=ffh, pwm=gray0 ioff1 supply current 400 200 100 - rindn pull down resistor % ? 3.0 ? 1.5 rext=500 ? iout=40 v , vout=1.5v iolpp1 output current1 pin to pin deviation ? 400 200 100 - rinup pull up resistor %/v ? 1.0 ? 0.5 rext=500 ? iout=40 v , vout=1.5v %/vdd output current vs. supply voltage regulation % ? 6.0 ? 3.0 rext=500 ? iout=40 v , vout=1.5v iolcc1 output current1 chip to chip deviation 0.8vdd ioh=1ma voh v 0.2vdd iol=1ma vol dout output voltage ua 1 voh=6.0v ioz output leakage current 0.3vdd gnd - vil l level 0.7vdd min. typ. vdd max. v - vih h level input voltage unit test condition symbol parameter dc characteristic test circuit v dd i dd LD1071 out0 out15 dout i ol rext gnd iref i in i ih i il v in v ih v il pwmck strobe din clock (note ) ref : constant current control value ( cr[7:0] of configuration register )
ver1.0 8 LD1071 16 channel output led driver with 14 bit pwm controller electrical characteristics (vdd = 3.3v, ta = 25 o c) 7.0 4.5 - rext=500 ? , outn=off ref=ffh, pwm=gray0 ioff2 ma 0.6 0.4 - rext=open, outn=off ref=ffh, pwm=gray0 ioff1 supply current 500 300 150 - rindn pull down resistor % ? 3.0 ? 1.5 rext=500 ? iout=36 v , vout=1.5v iolpp1 output current1 pin to pin deviation ? 500 300 150 - rinup pull up resistor %/v ? 1.0 ? 0.5 rext=500 ? iout=36 v , vout=1.5v %/vdd output current vs. supply voltage regulation % ? 6.0 ? 3.0 rext=500 ? iout=36 v , vout=1.5v iolcc1 output current1 chip to chip deviation 0.8vdd ioh=1ma voh v 0.2vdd iol=1ma vol dout output voltage ua 1 voh=6.0v ioz output leakage current 0.3vdd gnd - vil l level 0.7vdd min. typ. vdd max. v - vih h level input voltage unit test condition symbol parameter dc characteristic test circuit v dd i dd LD1071 out0 out15 dout i ol rext gnd iref i in i ih i il v in v ih v il pwmck strobe din clock (note ) ref : constant current control value ( cr[7:0] of configuration register )
ver1.0 9 LD1071 16 channel output led driver with 14 bit pwm controller ac characteristic test circuit v dd strobe din LD1071 out0 out15 dout rext gnd sw-matrix clock vdd gnd c l v l r l c l pwmck parameter symbol test condition unit propagation delay time (?l? to ?h?) t plh ns max. 20 typ. 10 min. - v dd = 5.0v v ih = vdd v il = gnd f ck = 10mhz r ext = 1590 ? i out = 19.1ma c l = 10.0pf r l = 150 ? vl = 4.5v switching characteristics (ta = 25 o c unless otherwise noted) clock-dout 50 - pwmck-outn - propagation delay time (?h? to ?l?) t phl ns 20 10 - clock-dout 30 - pwmck-outn - maximum clock frequency f ckmax (*1) mhz 25 10 - data set up time t setup (d) ns - 15 10 data hold time t hold (d) - 15 10 - 15 10 lh - 15 hl 10 strobe set up time ns t stb setup - - 10 lh - - hl 10 strobe hold time ns t stb hold maximum clock rise time t r 30 - - ns maximum clock fall time t f 30 - - output rise time (outn) t or 30 - - ns output fall time (outn) t of 30 - - *1 : cascade operation maximum pwmck frequency f pwmckmax (*1) mhz 25 8 - pulse width t wh0 / t wl0 ns - 20 15 clock t wh1 ns - 20 15 pwmck t wh2 ns - 20 15 strobe global latch set up time tglc ns - - 20
ver1.0 10 LD1071 16 channel output led driver with 14 bit pwm controller timing waveform clock-strobe pwmck-outn strobe h l clock t stb setup t stb hold 50% 50% h l 50% 50% strobe t stb setup t stb hold 50% h l 50% 50% 50% t wh2 t phl t plh 50% 50% 50% 50% h l off on pwmck outn t wh1 50% clock-din-dout t r t f h l h l clock din dout t phl t wh0 t setup t hold t or t of t plh 90% 50% 10% 90% 50% 10% 90% 50% 10% 90% 50% 10% 50% 50% 50% h l t wl0
ver1.0 11 LD1071 16 channel output led driver with 14 bit pwm controller equivalent circuit of inputs and outputs 1. pwmck terminal vdd pwmck gnd 2. strobe terminal vdd strobe gnd 3. clock, din terminal vdd gnd 4. dout terminal vdd (data) gnd clock, din dout
ver1.0 12 LD1071 16 channel output led driver with 14 bit pwm controller functional description command table this command is used to check the ?open/short? error status of led. 003ch error status read command this command is used to deliver the in ternal display data register outputs latched by display data write command to the internal pwm comparator to make an output current. the global latch command should be transferred after sending the final display data you want. the global latch command has no command value but it needs a special execution sequence. - global latch command this command is used to read the st atus of configur ation register. 0038h configuration register read command this command is used to update the c ontents of configur ation register. 0034h configuration register write command this command is used to write the display image data into led driver ic for display system. 0084h display data write command this command should be issued after power supply input. the configuration register, internal shi ft register, display data register will be cleared with ?0? states. 0001h software reset command description command value command name
ver1.0 13 LD1071 16 channel output led driver with 14 bit pwm controller configuration register read command (0038h) configuration register write command (0034h) clock din strobe dout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 14 15 16 17 18 c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 c1 4 c15 d0 d1 d2 d14 d15 d16 d17 d18 !5 !5 !5 !5 !5 !5 previous data msb lsb 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 c0 c1 c2 c14 c15 d0 d1 d2 timing diagram of command control software reset command (0001h) clock din strobe dout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 c1 4 c15 d0 d1 d2 d14 d15 d16 d17 d18 !5 !5 !5 !5 !5 !5 previous data msb lsb 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c0 c1 c2 c14 c15 d0 d1 d2 error status read command (003ch) clock din strobe dout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 14 15 16 previous data msb lsb 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 clock din strobe dout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 14 15 16 !5 !5 !5 !5 !5 previous data msb lsb 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 er15 er14 er13 er1 er0 !5 c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 c1 4 c15 don?t care !5 !5 !5 !5 !5 !5 c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 c1 4 c15 don?t care cr15 cr14 cr13 cr1 cr0
ver1.0 14 LD1071 16 channel output led driver with 14 bit pwm controller global latch command display data write command (0084h) clock din strobe dout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 14 15 16 17 18 !5 !5 !5 !5 !5 previous data msb lsb 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 c0 c1 c2 c14 c15 d0 d1 d2 msb lsb c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 c1 4 c15 d0 d1 d2 d14 d15 d16 d17 d18 !5 clock din strobe 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 252 253 254 255 256 257 258 dout d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 d252 d253 d254 d255 d0 d1 d2 !5 !5 out1 ~ out15 display data !5 !5 !5 !5 previous data d240 d241 d242 one chip data case *1) out0 display data total 16 strobes for 16 output ports data [ note *1 ] the number of clocks in global latch command can be extended from 8 to16. clock din strobe 8 9 10 11 12 13 14 15 16 nth chip display data write command out0 display data 1 2 3 4 5 6 7 8 d7 d8 d9 d10 d11 d12 d13 d14 d15 don? t care global latch command *1) global latch command execution ( internal ) t glc t glc t glc [ note *1 ] for the cascaded multi-chip configuration case, refer to ?display data write? timing diagram, please.
ver1.0 15 LD1071 16 channel output led driver with 14 bit pwm controller constant current control (cr[7:0] default 00h ) the iout is a constant current of outn po rt which is determined by rext resistor. configurtion register ( cr[15:0] ) error detection mode ( cr[9:8] default 00b ) short check 0 1 check disable 1 1 open check 1 0 check disable 0 0 error mode bit8 bit9 global latch mode automatic synchronization 1 one shot 0 global latch mode bit10 ( cr[10] default 0b ) constant current control (ref) error detection mode global latch mode reserved iout 1 1 1 1 1 1 1 1 - - - - - - - - - iout*255/256 0 1 1 1 1 1 1 1 iout*128/256 1 1 1 1 1 1 1 0 iout*2/256 1 0 0 0 0 0 0 0 iout/256 0 0 0 0 0 0 0 0 - - - - - - - - - current value bit7 bit6 bit5 bit4 bit0 bit1 bit2 bit3 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
ver1.0 16 LD1071 16 channel output led driver with 14 bit pwm controller when global latch command is executed in this mode, the LD1071 will update the next image data into output ports immediately, no matter what the counting status of previous image data is. the 14 bit internal pwm counter is initialized with 0000h and the internal pwm counter starts counting with pwmck clock. when the internal pwm counter value is reach ed to ffffh, the internal pwm count er stops the counting even next pwmck clock is inputting continuously. as a result, all the outputs will be stopped after finishing one internal pwm display cycle (16384 pwmck clocks). only the next global latch command can initialize the counting again. one shot mode ( default ) automatic synchronization mode synchronization for pwm counting the LD1071?s global latch command supports two kinds of synchronization mode for pwm counting. the default mode is one shot mode( configuration register bit10=0 ) and the other mode is automatic synchronization mode( configuration register bit10=1 ). when global latch command is executed in this mode( global latch mode=1 ), the LD1071 will update the next image data into output ports immediately, no matter what the counting status of previous image data is. when the internal pwm counter value is reached to ffffh, if there is no global latch command, the LD1071 automatically loads the previous image data into output ports at next 16384 th pwmck clock again. so in this mode, output ports will be automa tically updated at every 16384 pw mck clocks with previous data. global latch command execution outn pwmck global latch command execution all outputs are disabled. all outputs are disabled. 1 2 16383 0 012 n n+1 n+2 16382 ( internal ) internal 14 bit pwm counter 01 02 16383 1 2 0 n 16383 16384 16384 16385 16386 all outputs are disabled. 16382 16383 16382 global latch command execution outn pwmck output ports are switching according to next data value. output ports are automatically loading according to the previous data value. ( internal ) internal 14 bit pwm counter 01 2 345 16383 012 nn+1n+2 nn+1 16383 012 n n+ 1 n+2 nn+1 16384 16385 16386 16387 16388 16389 all outputs are disabled.
ver1.0 17 LD1071 16 channel output led driver with 14 bit pwm controller writing the display data with the 16 bit data, all output ports can be built with 16,384 gray scales. the 16-bit input shift register latches 16 times of gray scale data into each data buffer with display data write command sequentially . finally global latch command will load the 256 bit internal data buffers with lsb first into from output port 15( out15 ) to output port 0( out0 ). even 16 bit display data for each port should be transferred, only 14 bits data are valid for gray scale image ( bit[13:0] ) and the high 2bits( bit[15:14] ) are reserved. for the detail timing and sequence, refer to ?display data write command? and ?global latch command? which is described on page 14, please. pwm display cycle the LD1071 implements the 14 bit gray level of each output port using the 4 pwm sub cycles. each pwm sub cycle is consisted of 12 bit pwmck clocks. this enhancement provides a excellent energy distribution in lighting the led and increases the visual refresh rate and reduces the flickers. d[15:14] : reserved d[13:0] : display data( 14 bit gray scale data ) bit[13:2] : 12bit pwm comparing data bit[ 1: 0] : pwm insert data 1 1 : one pulse is inserted in 1st, 2nd and 3rd pwm sub cycle 1 0 : one pulse is inserted in 1st and 2nd pwm sub cycle 0 1 : one pulse is inserted in 1st pwm sub cycle 0 0 : not inserted 12bit pwm 4096 pwmck clocks 1st pwm sub cycle 2nd pwm sub cycle 3rd pwm sub cycle 4th pwm sub cycle 12bit pwm 4096 pwmck clocks 12bit pwm 4096 pwmck clocks 12bit pwm 4096 pwmck clocks on off on off on off on off out[15:0] 1 pwm cycle ( 14 bit pwm display = 16384 pwmck clocks = 4096 x 4 )
ver1.0 18 LD1071 16 channel output led driver with 14 bit pwm controller ( case 1 ) the following examples show the pwm timing diagram for different display data. 1 pwm cycle ( = 16384 pwmcks = 4096 x 4 ) 1st pwm sub cycle 2nd pwm sub cycle 3rd pwm sub cycle 4th pwm sub cycle out[15:0] out[15:0] out[15:0] out[15:0] on off on off on off on off 2048 pwmcks 2048 pwmcks 2048 pwmcks 2047 pwmcks 2048 pwmcks 2048 pwmcks 2047 pwmcks 2047 pwmcks 2048 pwmcks 2047 pwmcks 2047 pwmcks 2047 pwmcks 2047 pwmcks 2047 pwmcks 2047 pwmcks 2047 pwmcks 1 pwm sub cycle ( 4096 pwmcks ) d[15:0] = 0001_1111_1111_1111b (1 6'h1fff) d[15:0] = 0001_1111_1111_1110b (16'h1ffe) d[15:0] = 0001_1111_1111_1101b (16' h1fffd) d[15:0] = 0001_1111_1111_1100b (16' h1fffc)
ver1.0 19 LD1071 16 channel output led driver with 14 bit pwm controller ( case 3 ) 1pwmck out[15:0] out[15:0] 1pwmck 1pwmck 1pwmck 1pwmck out[15:0] 1pwmck out[15:0] 1st pwm sub cycle 2nd pwm sub cycle 3rd pwm sub cycle 4th pwm sub cycle d[15:0] = 0000_0000_0000_0011b (16'h0003) d[15:0] = 0000_0000_0000_0010b (16'h0002) d[15:0] = 0000_0000_0000_0001b (16'h0001) d[15:0] = 0000_0000_0000_0000b (16'h0000) 1 pwm cycle ( = 16384 pwmcks = 4096 x 4 ) 1 pwm sub cycle ( 4096 pwmcks ) ( case 2 ) 2 pwmcks out[15:0] out[15:0] 2 pwmcks 2 pwmcks out[15:0] out[15:0] 1pwmck 2 pwmcks 2 pwmcks 1pwmck 1pwmck 2 pwmcks 1pwmck 1pwmck 1pwmck 1pwmck 1pwmck 1pwmck 1pwmck 1st pwm sub cycle 2nd pwm sub cycle 3rd pwm sub cycle 4th pwm sub cycle d[15:0] = 0000_0000_0000_0111b (16'h0007) d[15:0] = 0000_0000_0000_0110b (16'h0006) d[15:0] = 0000_0000_0000_0101b (16'h0005) d[15:0] = 0000_0000_0000_0100b (16'h0004) 1 pwm cycle ( = 16384 pwmcks = 4096 x 4 ) 1 pwm sub cycle ( 4096 pwmcks )
ver1.0 20 LD1071 16 channel output led driver with 14 bit pwm controller ( case 5 ) out[15:0] out[15:0] 4095 pwmcks out[15:0] out[15:0] 4094 pwmcks 4095 pwmcks 4095 pwmcks 4094 pwmcks 4094 pwmcks 4094 pwmcks 4094 pwmcks 1st pwm sub cycle 2nd pwm sub cycle 3rd pwm sub cycle 4th pwm sub cycle d[15:0] = 0011_1111_1111_1011b (16'h3ffb) d[15:0] = 0011_1111_1111_1010b (16'h3ffa) d[15:0] = 0011_1111_1111_1001b (16'h3ff9) d[15:0] = 0011_1111_1111_1000b (16'h3ff8) 4094 pwmcks 4094 pwmcks 4095 pwmcks 4095 pwmcks 4094 pwmcks 4094 pwmcks 4094 pwmcks 4095 pwmcks 1 pwm cycle ( = 16384 pwmcks = 4096 x 4 ) 1 pwm sub cycle ( 4096 pwmcks ) ( case 4 ) out[15:0] out[15:0] 4096 pwmcks out[15:0] out[15:0] 4095 pwmcks 4096 pwmcks 4096 pwmcks 4095 pwmcks 4095 pwmcks 4095 pwmcks 4095 pwmcks 1st pwm sub cycle 2nd pwm sub cycle 3rd pwm sub cycle 4th pwm sub cycle d[15:0] = 0011_1111_1111_1111b (1 6'h3fff) d[15:0] = 0011_1111_1111_1110b (16'h3ffe) d[15:0] = 0011_1111_1111_1101b (16'h3ffd) d[15:0] = 0011_1111_1111_1100b (16'h3ffc) 4095 pwmcks 4095 pwmcks 4096 pwmcks 4096 pwmcks 4095 pwmcks 4095 pwmcks 4095 pwmcks 4096 pwmcks 1 pwm cycle ( = 16384 pwmcks = 4096 x 4 ) 1 pwm sub cycle ( 4096 pwmcks )
ver1.0 21 LD1071 16 channel output led driver with 14 bit pwm controller error detection code open check output port status error detection voltage meaning off out voltage > 0.8v normal out voltage < 0.8v open error short check off out voltage > 0.8v normal out voltage < 0.8v short error error status register ( er[15:0] ) bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 out15 out14 out13 out12 out11 out10 out9 out8 out7 out6 out5 out4 out3 out2 out1 out0 16 bit shifter register dout error status read command 0 : normal 1 : open or short error - open error : output port( outn ) is not connected to led. - short error : output port( outn ) is shorted to gnd. error detection the LD1071 will be able to detect the error status of led such as open/short e rror. this function can be entered by setting the bits of error detection mode( cr[9:8] ) as 01b( open detection ) or 10b( short detection ). the correct meaning of error is defined as follows; timing diagram of error status check note *1) in order to keep the constant current value( cr[7:0] ) and global latch mode( cr[10] ) correctly, maybe you need to read the configuration register through the configuration register read command( 0038h ) prior to set error detection mode. clock din strobe dout pwmck outn !5 previous data !5 2 115161215 16 !5 c1 c0 c15 d1 d0 d15 !5 !5 !5 !5 2 134131415 16 c1 c0 c3 !5 !5 !5 12 3 15 16 !5 14 don?t care er15 er14 er13 er1 er0 error status read command set error detection mode 0034h 003ch d[9:8] *1) !5 !5 actual read operation the next timing diagram shows the sequence of error status read operation. the actual error status is read with msb first after execution of error status read command. first of all, in order to read the error status, all the output ports (out15~ out0) should be off. so you n eed some pre-processing for error status read. the flow chart will be provided on next page. c13 c15 c2 c14
ver1.0 22 LD1071 16 channel output led driver with 14 bit pwm controller 1) set display data write command( 0084h ) with 0000h data 2) run totally 16 times for all the 16 output ports off ( 1 chip ) 3) if n-chips are cascaded, repeat 1) and 2)?s operations n times set all output ports off start run global latch command 1) set configuration register write command( 0034h ) - cr[9:8] = 01 : open detection, 10 : short detection 2) if n-chips are cascaded, repeat 1)?s operations n times set error detection mode 1) set error status read command( 003ch ) 2) if n-chips are cascaded, repeat 1)?s operations n times run error status read command 1) input 16 clocks to read the error status of chip1. the error status of port15 will be outputted at fall edge first. 2) if n-chips are cascaded, input n x 16 clocks to read error status of all ports( n x 16 ports ). the data of last chip( nth chip ) will be outputted first. input clocks end flow chart of error status check
ver1.0 23 LD1071 16 channel output led driver with 14 bit pwm controller configuration register write( current control ) configuration register read 0038h 0038h 0038h 0038h 0000h 0000h 0000h 0000h strobe din clock xxxxh xxxxh xxxxh xxxxh 001ah 002bh 003ch 004dh dout configuration register write (error detection enable) 0034h 0034h 0034h 0034h 011ah 012bh 013ch 014dh strobe din clock xxxxh xxxxh xxxxh xxxxh 0034h 0034h 0034h 0034h dout 0034h 0034h 0034h 0034h 001ah 002bh 003ch 004dh strobe din clock xxxxh xxxxh xxxxh xxxxh 0034h 0034h 0034h 0034h dout command setting guide for mult i-chip cascade configuration strobe clock din clock strobe din dout clock strobe din dout clock strobe din dout clock strobe din dout 1st chip 2nd chip 3rd chip 4th chip dout
ver1.0 24 LD1071 16 channel output led driver with 14 bit pwm controller error status read 003ch 003ch 003ch 003ch 0000h 0000h 0000h 0000h strobe din clock xxxxh xxxxh xxxxh xxxxh err4 err3 err2 err1 dout software reset nop operation 0001h 0001h 0001h 0001h strobe din clock xxxxh xxxxh xxxxh xxxxh dout 0000h 0000h 0000h 0000h xxxxh xxxxh xxxxh xxxxh software reset & nop operation display data write 0084h 0084h 0084h 0084h data1 data2 data3 data4 strobe din clock xxxxh xxxxh xxxxh xxxxh 0084h 0084h 0084h 0084h dout out0 display data of each chip
ver1.0 25 LD1071 16 channel output led driver with 14 bit pwm controller power up software reset command configuration register write (set constant current) display data write graphics is displayed the first command should be issued after 0.1ms from power-up. recommendation of global sequence global latch display data write graphics is displayed global latch
ver1.0 26 LD1071 16 channel output led driver with 14 bit pwm controller the output current is determined by an external resistor. the relationship between i out and r ext is as follows; setting output current -r ext : external resistor[ ? ] - ref : constant current control (0 ~ 255, cr[7:0] of conf iguration register) i out [a] = {1.06/(120+r ext )} * s * 61.4 where s = (ref+1)/512 when vdd = 5v when vdd = 3.3v i out [a] = {1.06/(150+r ext )} * s * 57.6 where s = (ref+1)/512 because the default ref value( cr[7:0] ) of configuration register( 0034h ) for current control is 00h, if you want to set the output current through changing the r ext value with following graph, do not forget to write the cr[7:0] of configuration register with ?ffh?, please. 7 %%7 3&95 ?
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vout = 2.0v 7%%7 3&95 ?
*065 n" [ note ] when vdd is 3.3v, in order to guarantee the accurate output current, do not set the iout to over 40ma, please.
ver1.0 27 LD1071 16 channel output led driver with 14 bit pwm controller constant output current the LD1071 provides a constant current output characteristics for led display application. the pin to pin deviation is max +/- 3% and chip to chip deviation is max +/- 6%. $potubou$vssfou0vuqvu 7065 7
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vdd=5v, rext=400, vout = 2.0v the LD1071 provides a excellent iout linearity by setting the configuration register for global brightness control. the following graph shows the linearity example under the condition at vdd=5v, rext=400 ohms and vout = 2.0v.
ver1.0 28 LD1071 16 channel output led driver with 14 bit pwm controller led supply voltage( vled ) !? !? v led v drop vf LD1071 v out !? !? v led v drop vf LD1071 v out r l it is very important to select the proper value of load resistor( rl ). because the optimal vout value guarantees the constant output current and long life time of led driver ic without over power consumption. for example, let?s calculate the load resistor value at vled=5v, iout=20ma, led forward voltage(vf)=3v. 1) the full current of ld1018 = 20ma x 16 (channels) = 320ma 2) the power consumption is 320ma x vout voltage. - when vout = 1v, the power consumption is 320mw. - when vout= 2v, the power consumption is 640mw. therefore, the load resistor (rl) = (vled ? vout? vf) / iout = (5v ? vout ? 3v) / 20ma = 40 ? (when vout = 1.2v)
ver1.0 29 LD1071 16 channel output led driver with 14 bit pwm controller package power dissipation( pd ) the LD1071 provides many package options such as 24-sop package and 24-ssop package. the maximum allowable package power dissipation is determined as pd(max) = (tj ? ta) / r_theta_ja. when 16 output ports are turned on simultaneously, the actual power package dissipation is pd(act) = (idd x vdd) + (iout x duty x vout x 16). therefore, to keep that pd(act) is less equal than pd(max). the maximum allowable output current as a function of duty cycle is: *pvuwt%vuz 401
%v uz *pvu n"
5b 5b 5b 5b ( r_theta_ja = 75c/w ) *p vuw t %vuz 4401
%v uz *pvu n"
5b 5b 5b 5b ( r_theta_ja = 85c/w ) i out = {[(tj ? ta) / r_theta_ja] ? (idd x vdd)} / v out / duty / 16 where tj = 150c 1bdlbhf1pxfs%jttjqbujpo "ncjfou5fnqfsbuvsf $
1pxfs%j ttj qbuj po 8
401 4401
ver1.0 30 LD1071 16 channel output led driver with 14 bit pwm controller application circuit 1 (16x2 static type) data & control signal connection for 16x2 static type application LD1071 out0 out15 r-ext out7 clock dout v dd pwmck strobe din out0 out15 r-ext gnd gnd out7 clock dout pwmck strobe din LD1071 din pwm strobe clock v dd v dd vdd vdd v led = 5v d00 d07 d015 i 0 i 7 i 15 r l r l r l v led = 5v d10 d17 d115 i 0 i 7 i 15 r l r l r l
ver1.0 31 LD1071 16 channel output led driver with 14 bit pwm controller timing diagram for application circuit 1 (default one shot mode) 16384 pwmclks ( display data write command ) ( 1st frame data ) clock din strobe pwmck 16 clocks 16 clocks (0084h) (0084h) ( display data write command ) ( 1st frame data ) d00 out0[15:0] (chip0) (chip1) (chip0) 16 clocks d10 out0[15:0] (chip1) (16 strobes) d015 out15[15:0] (chip0) ( global latch ) 16 clocks 16 clocks ( display data write command ) 16 clocks 16 clocks (0084h) (0084h) ( 2nd frame data ) d00 out0[15:0] (chip0) (chip1) (chip0) 16 clocks d10 out15[15:0] (chip1) (16 strobes) d015 out15[15:0] (chip0) ( global latch ) 16 clocks 16 clocks outn 16384 pwmclks (1st frame display) (2nd frame display) outn (1st frame display)
ver1.0 32 LD1071 16 channel output led driver with 14 bit pwm controller controller r vled = 5v r l r l r l vdd vdd r l r l r l r l r l r l pnp pnp r 4 r 5 q15 pnp pnp r 4 r 5 q1 pnp pnp r 4 r 5 q0 d00 d01 d015 d10 d11 d115 d150 d151 d1515 data clk stb pwm application circuit 2 (16x16 dynamic type) din clock strobe pwmck vdd dout r-ext gnd out0 out1 out15 LD1071 s0 s1 s15 data & control signal connection for 16x16 dynamic type application
ver1.0 33 LD1071 16 channel output led driver with 14 bit pwm controller timing diagram for application circuit 2 (default one shot mode) outn outn 16384 pwmclks s0 s1 s2 ( 1st line data ) clock din strobe pwmck ( global latch ) 2nd line display 3rd line display ( display data write command ) ( 3rd line data ) 16 clocks 16 clocks (0084h) d20 (16 strobes) d215 out15[15:0] ( global latch ) 16 clocks ( display data write command ) (4th line data ) 16 clocks16 clocks (0084h) d30 d315 out15[15:0] ( global latch ) 16 clocks (16 strobes) ( display data write command ) 16 clocks 16 clocks (0084h) d00 (16 strobes) d015 out15[15:0] 16 clocks (2nd line data ) 16 clocks16 clocks (0084h) d10 d115 out15[15:0] ( global latch ) 16 clocks (16 strobes) ( display data write command ) 16384 pwmclks 16384 pwmclks 1st line display out0[15:0] out0[15:0] out0[15:0] out0[15:0]
ver1.0 34 LD1071 16 channel output led driver with 14 bit pwm controller LD1071-sp (sop 24) package information
ver1.0 35 LD1071 16 channel output led driver with 14 bit pwm controller LD1071-ss (ssop 24 ? 150)
ver1.0 36 LD1071 16 channel output led driver with 14 bit pwm controller the products listed herein are designed for ordinary el ectronic applications, such as electrical applications, audio-visual equipment, communications devices and so on. hence, it is advisable that the devices should not be used in medical instrument, surgical implants, aerospace machinery, nuclear power control systems, disaster/crime-prevention equipment and the like. misusing those products may directly or indirectly endanger human life, or cause injury and property loss. ldt will not take any responsibiliti es regarding the misusage of the produ cts mentioned above. anyone who purchases any products described herein with the above-me ntioned intention or with such misused application should accept full responsibilit y and indemnify. ldt and its distributor s and all their officers and employees shall defend jointly and severally against any and all clai ms and litigation and all damages, cost and associated with such intention and manipulation.

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